That would be most of the logic to be simulated d) For each process P, if P is currently sensitive to a signal S and ifĪn event has occurred on S in this simulation cycle, then P resumes.This should be the signals with a new projected value such as signals delayed by the after. b) Each active explicit signal in the model is updated.The following sections from the LRM may seem to support this theory:Ī simulation cycle consists of the following steps: The later is said to be better, because it is scheduled before any process is executed, and thus signals that are changed synchronously to the clk edge are handled properly. On other cases I see: clk <= not clk after 10 ns In many test benches I see the following pattern for clock generation:
